(1). Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making more reliable field effect transistors (FETs) having less leakage current. The method utilizes a composite sidewall spacer consisting of a trapezoidal-shaped silicon oxide (SiO.sub.2) spacer and a silicon nitride (Si.sub.3 N.sub.4) spacer that reduces substrate damage in the source/drain contact areas during plasma etching.
(2). Description of the Prior Art
One type of semiconductor device commonly used for Ultra Large Scale Integration (ULSI) is the Field Effect Transistor (FET). These FETs are preferred because of their small size, high packing density, low power consumption, high yields, and low manufacturing cost. FET devices are fabricated on single-crystal silicon substrates by forming a thin gate oxide, depositing a polysilicon or polycide layer and patterning to form gate electrodes. Then self-aligned source/drain contact (SAC) areas are formed in the substrate adjacent to the gate electrodes. For narrow channel FETs, to eliminate undesirable short-channel effects, it is common practice to include lightly doped source/drain areas and sidewall spacers before forming the self-aligned heavily doped source/drain contact areas. The gate electrodes are themselves used as implant barrier masks to form the self-aligned lightly doped source/drain areas, commonly referred to as the LDD areas.
Unfortunately, several problems arise during processing that degrade the FET device. One of the problems that arises during directional plasma etching to form the sidewall spacers is that ion damage to the shallow diffused source/drain areas results in higher leakage currents when the device is powered up. The sidewall spacers are typically formed by anisotropically etching back a Si.sub.3 N.sub.4. However, it is necessary to use a thin SiO.sub.2 layer (a stress-release layer) to minimize the stress between the Si.sub.3 N.sub.4 and the silicon substrate. When this SiO.sub.2 layer is removed from the source/drain areas by wet etching, the SiO.sub.2 can be eroded along the sidewalls of the gate electrodes which degrades device performance and reliability.
A method for making a patterned second polysilicon layer over a patterned first polysilicon layer (such as a gate electrode) without leaving residue (stringers) that would otherwise occur during directional plasma etching is described in U.S. Pat. No. 5,656,533 to Kim. Kim's patent does not address the above problem. Ahmad et al. in U.S. Pat. No. 5,405,791 teach a method for making N-channel and P-channel FETs using disposable sidewall spacers and using a Si.sub.3 N.sub.4 cap layer over the FETs, but do not address the above problems. In U.S. Pat. No. 5,824,588 to Liu, a method is described for making a double-sidewall salicide MOS device. The method uses a first sidewall spacer that is higher than the gate electrode to prevent short circuiting between the gates and the source/drain areas. The second sidewall spacer is used to form the LDD regions. Yu in U.S. Pat. No. 5,747,373 teaches a method for making a salicide FET using a double-sidewall spacer to prevent thinning of the first spacer during precleaning of the substrate surface, and thereby eliminate electrical shorting between the gate electrodes and the source/drain areas when a metal is deposited and annealed to form the salicide FET.
Therefore, there is still a strong need in the semiconductor industry to fabricate more reliable FETs using a process that minimizes or eliminates plasma damage to the source/drain contacts, and prevents erosion of the thin SiO.sub.2 stress-release layer along the gate electrodes when a wet etch is used to remove the stress-release layer on the source/drain contact areas.